logisim-evolution/logisim-evolution
Digital logic design tool and simulator
A star delta has been computed for 61,707 of 62,640 tracked repositories in this period, and only those can be ranked in it.
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Star counts measured between 17:21 and 08:49 (BKK).
Digital logic design tool and simulator
cocotb: Python-based chip (RTL) verification
Modular hardware build system
SystemVerilog compiler and language services
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Veryl: A Modern Hardware Description Language
🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Control and status register code generator toolchain
XLS: Accelerated HW Synthesis
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
:seedling: Open source ecosystem for open FPGA boards
Package manager and build abstraction tool for FPGA/ASIC development
Verilog/SystemVerilog support for VS Code
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
:snowflake: Visual editor for open FPGA boards
Verilator open-source SystemVerilog simulator and lint system
That's all 18 repositories in this period.