openwall/john
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
A star delta has been computed for 62,678 of 63,382 tracked repositories in this period, and only those can be ranked in it.
A repository missing here has not been measured far enough back yet. That does not mean it did not move.
Star counts measured between 08:09 and 19:27 (BKK).
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
Build your hardware, easily!
Universal utility for programming FPGA
Digital logic design tool and simulator
Control and status register code generator toolchain
Scots Army Knife for electronics
Machine learning on FPGAs using HLS
:seedling: Open source ecosystem for open FPGA boards
SDK for FPGA / Linux Instruments
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
An Open-source FPGA IP Generator
Modular hardware build system
SystemRDL 2.0 language compiler front-end
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Brevitas: neural network quantization in PyTorch
Dataflow compiler for QNN inference on FPGAs
PandA-bambu public repository
🕹 A zero-setup ROM collection manager that sorts, filters, extracts or archives, patches, and reports on collections of any size on any OS.
PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Package manager and build abstraction tool for FPGA/ASIC development
Next Generation IDE for Electronics Development
Build Customized FPGA Implementations for Vivado
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Allo Accelerator Design and Programming Framework (PLDI'24)
:snowflake: Visual editor for open FPGA boards
Run Time for AIE and FPGA based platforms
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
That's all 30 repositories in this period.
